VHDL Compiler ٤+

Name: VHDL Compiler
Rating: 2.7 (7 reviews)
Author: Ketan Appa

Ketan Appa

- ٢٫٧ - ٧ من التقييمات

- مجانًا
- يوفر عمليات الشراء داخل التطبيق

الوصف

Write VHDL code directly on your iPhone, iPad and iPod Touch! This app is ideal for learning and testing code snippets!

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

This app uses the open-source GHDL simulator (http://ghdl.free.fr). GHDL is a VHDL compiler that can execute (nearly) any VHDL program. GHDL is not a synthesis tool: you cannot create a netlist with GHDL (yet).

Features:
- Compile and run your program
- View program output or detailed error
- Custom keyboard for easy input of frequently used characters
- Optimized for connecting with external physical/bluetooth keyboard
- Advanced source code editor with syntax highlighting and line numbers
- Open, save, import and share VHDL files.

Limitations:
- Internet connection is required for compilation
- Maximum program running time is 20s
- One file can be run at a time
- All entities should be have the same name as their files.

٣ نوفمبر ٢٠٢٤

الإصدار 2.3.1

Bug fix when using keyboard shortcut on iPad

٢٫٧ من ٥

٧ من التقييمات

Works great simulates std_logic circuits just fine

I realized that it’s essential to limit simulation with ultimately a WAIT; statement including a clock generator with limited total time
Here is a simple test setup beyond just text:

Enjoy.. great job by the developer of the App and the original open source VHDL Compiler Designer
————————————————
-- Hello world program
library IEEE;
use IEEE.std_logic_1164.all;

use std.textio.all; -- Imports the standard textio package.

-- Defines a design entity, without any ports.
entity hello is
end hello;

architecture behaviour of hello is

signal index : integer:=0;
signal clk : std_logic := '0';
begin
process(clk)
variable l : line;
begin
if(rising_edge(clk)) then
write(l,String'("/"));
writeline (output, l);
end if;
end process; process

begin
index <= index +1;
clk <= not clk;
wait for 1 ns;
if index > 20 then
wait;
end if;
end process;
end behaviour;

أوضح المطور Ketan Appa، أن ممارسات خصوصية التطبيق قد تتضمن معالجة البيانات على النحو الموضح أدناه. لمزيد من المعلومات، انظر %سياسة خصوصية المطور(ة) سياسة خصوصية المطور.