Version 1.6 adds a new starting point for exploring logic: • Derive the truth table, Karnaugh map, and corresponding circuit from a Boolean expression written as text. • Fixed an issue with circuit generation from a truth table.

Version 1.5.1 improves several features: • Layered selection for wires (wire, segment, vertex), plus new Join Wires (⌘J) and Split Here commands • More precise snapping and alignment, especially on junctions and wire endpoints • Junctions are created only where needed and always follow the wires • Press ⇧ to free the angle of wires • Context menus now show only relevant options • Timing diagram fixes and an updated manual Version 1.5 expands Circuit Deck from drawing schematics to describing how blocks behave. • A new VHDL editor sits beside the canvas, with syntax highlighting, line numbers, indentation, and errors identified by position. Ports in the code become the block’s pins. • VHDL blocks can now take part in circuit simulation, including sequential logic and clock edges. This is logical simulation of supported constructs: Circuit Deck is not a full VHDL simulator and does not implement delta cycles. • Simulation now supports buses and multibit values, registers, counters, and ALUs. Bus values appear directly on the schematic. • Output calculation in timing diagrams and input sampling at clock edges have been improved. • Several issues with drawing, wire connections, and VHDL editing have been fixed.

Version 1.5 expands Circuit Deck from drawing schematics to describing how blocks behave. • A new VHDL editor sits beside the canvas, with syntax highlighting, line numbers, indentation, and errors identified by position. Ports in the code become the block’s pins. • VHDL blocks can now take part in circuit simulation, including sequential logic and clock edges. This is logical simulation of supported constructs: Circuit Deck is not a full VHDL simulator and does not implement delta cycles. • Simulation now supports buses and multibit values, registers, counters, and ALUs. Bus values appear directly on the schematic. • Output calculation in timing diagrams and input sampling at clock edges have been improved. • Several issues with drawing, wire connections, and VHDL editing have been fixed.